The present invention relates generally to integrated circuit designs, and more particularly to a power control circuit for down-shifting a supply voltage of an integrated circuit module depending on various operation modes.
Random access memory (RAM) is typically used for temporary storage of data in a computer system. There are several types of RAM, including dynamic random access memory (DRAM) and static random access memory (SRAM). SRAM retains its memory state without the need of any data refresh operations as long as it is supplied with power. A SRAM device is comprised of an array of “cells,” each of which retains one “bit” of data. A typical SRAM cell may include two cross coupled inverters and two access transistors connecting the inverters to complementary bit-lines. The two access transistors are controlled by word-lines to select the cell for read or write operation. In read operation, the access transistors are switched on to allow the charges retained at storage nodes of the cross coupled inverters be read via the bit line and its complement. In write operation, the access transistors are switched on and the voltage on the bit line or the complementary bit line is raised to a certain level to flip the memory state of the cell. Conventionally, the cell is designed to operate with a down-shifted supply voltage in the write operation than in the read operation in order to increase the write margin.
FIG. 1 shows one type of conventional circuit 100 for down-shifting the power supplied to an array of SRAM cells during write operation. A power control circuit 110 is connected to a core supply voltage (CVDD) and provides an intermediate supply voltage (CVDDi) to the SRAM array 120. A signal A controls PMOS transistor P1, such that CVDDi output from the power control circuit 110 can switch between CVDD and a lower voltage depending on the operation mode of the SRAM array 120. In read operation, signal A is designed to be a logic “low” that turns on the PMOS transistor P1, thereby passing CVDD to the SRAM array 120 without a substantial voltage drop. In such case, CVDDi substantially equals CVDD. In write operation, signal A is designed to be a logic “high” that turns off the PMOS transistor P1, thereby forcing power to pass through MOS diode P2 with a substantial voltage drop. In such case, CVDDi is lower than CVDD by a voltage drop across MOS diode P2. The lower CVDDi increases the write margin for the cells within the SRAM array 120.
One skilled in the art of SRAM design would appreciate that it takes a relatively long time for the PMOS transistor P1 to be completely turned off during the write operation. As a result, the response time of the power control circuit 110 is slow, which in turn, degrades the performance of the SRAM array 120.
As such, what is needed is a power control circuit that lowers a supply voltage in a short response time for an integrated circuit module that requires the supply voltage to be varied at different levels depending on various operation modes.